M.S (By Research)
Obtained her B.Sc degree from Bangalore University. Secured University 8th Rank
Obtained her M.Sc (Physics) degree from Bangalore University. Secured University 2nd Rank
Obtained her M.S (By Research) degree from VIT University, Chennai Campus. She was the first research student in SENSE to obtain the degree from this campus. The area of research being Memory Design and Testing.
She has also completed a Proficience course on Embedded System Design rom IISc, Bangalore.
She has a total teaching experience of 27 years with 17 years at PESIT/PES University. She has taught a variety of subjects at both UG and PG level. Her current interest is in the VLSI domain.
She has been handling various administrative responsibilities such as
- Time-Table Officer
- Class incharge
- Lab Incharge
- Faculty advisor and Test Co-ordinator to name a few.
Teaching : Total teaching experience is 27 years.
Taught a variety of subjects at both UG and PG level. She was invited to deliver guest lectures at various Institutions like Don Bosco Institute of Technology, PESIT South Campus etc. Her teaching has always been appreciated by her students which is reflected in the student feedback which has always been above 90%.
Obtained her M.S (By Research) degree from VIT University, Chennai Campus. Her research domain is VLSI and the topic of her thesis was " Error Detection and Correction in Memory".
Currently she is pursuing her Ph.D in the area of Analog VLSI. She has guided many student projects, a few of which are have been converted to conference papers.
1. Sunita, M.S and Kanchana Bhaaskaran V.S (2013). Matrix Code based multiple error correction technique for n-bit memory data, Int. Journal of VLSI Design and Communication Systems (VLSICS), Vol. 4, No.1, pp 29-37.
2. Sunita, M.S., Kanchana Bhaaskaran, Deepakakumara Hegde and Pavan Dhareshwar (2013). Error Detection and Correction in Embedded Memories using Cyclic Codes, Proc. of the Int. Conf. on VLSI, Communication, Advanced devices, Signals & Systems and Networking, (VCASAN), Lecture Notes in Electrical Engineering, Springer India, Vol. 258, Chap. 16, pp. 109-116.
3. Sunita, M.S., V.Chiranth, H.C. Akash and Kanchana Bhaaskaran V.S (2015). Pipeline Architecture for fast decoding of BCH Codes for NOR Flash Memory, ARPN Journal of Engineering and Applied Sciences, Vol. 10, No. 8, pp. 3397-3404.