Jayashree H V obtained BE degree in Electronics and Communication Engineering from DSCE, Bangalore and M.Tech in VLSI Design and Embedded systems from PESIT, Bangalore. She is currently pursuing research in VLSI domain under VTU. She has 12 years experience in academics and 1 year in Industry.
Her academic achievements include securing MRD award for being one among the toppers in M.Tech. She has carried out one year Internship at Intel India Pvt Ltd on performance and Functional verification of digital circuits, which includes various pre silicon verification stages. She has guided various projects in VLSI domain, outcome of the projects resulted in publication in peer reviewed conferences or Journals.
She is a member of IET and IEEE. Apart from teaching, research, and administrative activities, she regularly serves as a reviewer to peer reviewed International Journals and Conferences.
She has delivered a talk on “VLSI AND IT’S OPPURTUNITIES IN INDUSTRY” in the preplacement workshop. She has organized and hosted several activities at the department level. She has actively worked in the community development program.
Her current research interests include SOC verification, Verifiable IP development, Reversible and Quantum Computing. Design and Verification of circuits and new architectures in emerging nano technologies.
1. She has published papers in proceedings of leading International Conferences and in proceedings of leading National Publications
2. She has published papers in proceedings of leading International Conferences and in proceedings of leading National Conferences. She has also published International peer reviewed Journals
1. Jayashree, H. V., Skanda Kotethota, and V. K. Agrawal. "Reversible circuit design for GCD computation in cryptography algorithms." International Journal of Circuit Theory and Applications 45.2 (2017): 242-259.
2. H. V. Jayashree, H.Thapliyal, H.R. Arabnia, V.K. Agrawal, “Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier”, The Journal of Supercomputing doi: 10.1007/s11227-016-1676-0
3. H.Thapliyal, H. V. Jayashree, A. N. Nagamani, H.R. Arabnia, "Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder", Springer Transactions on Computational Science XVII Lecture Notes in Computer Science Volume 7420, 2013, pp 73-97.
4. Jayashree HV,Rohit Atvale and Tejas N ” Multi-UART Controller with Programmable Modes of Operation”,International Journal of Mechanical and Industrial Engineering (IJMIE), ISSN No. 2231 – 6477, Volume-1, Issue-2, 2011.
1. Jayashree, H. V., Himanshu Thapliyal, and Vinod Kumar Agrawal. "Efficient Circuit Design of Reversible Square." Transactions on Computational Science XXIX. Springer Berlin Heidelberg, 2017. 33-46.
IEEE CONFERENCE PUBLICATIONS:
1. Jayashree, H.V.; Surhonne, A.P.; Agrawal, V.K., "Performance trade-off in decision diagram based synthesis of reversible logic circuits," in Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on , vol., no., pp.209-212, 1-4 June 2015
Jayashree, H.V.; Ashwin, S.; Agrawal, V.K., "Berger check and fault tolerant reversible arithmetic component design," in Electron Devices and Solid-State Circuits (EDSSC), 2015 IEEE International Conference on , vol., no., pp.656-659, 1-4 June 2015
2. Jayashree, H.V.; Agrawal, V.K.; Bharadwaj, S.N., "Quantum cost realization of new reversible gates with transformation based synthesis technique," in VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on , vol., no., pp.1-6, 8-10 Jan. 2015
3. Jayashree, H.V.; Thapliyal, H.; Agrawal, V.K., "Design of Dedicated Reversible Quantum Circuitry for Square Computation," in VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on , vol., no., pp.551-556, 5-9 Jan. 2014
4. Jayashree, H.V.; Agrawal, V.K.; Kumari, D., "Quantum cost realization of new reversible functions using ESOP based synthesis," in Contemporary Computing and Informatics (IC3I), 2014 International Conference on , vol., no., pp.1330-1335, 27-29 Nov. 2014
Jayashree, H.V.; Harsha, K.; Kaushik, M.; Anusha, K.; Divya, B.M., "Design and performance analysis of low power ternary ADC for wide band communication," in Circuits, Systems, Communication and Information Technology Applications (CSCITA), 2014 International Conference on , vol., no., pp.24-29, 4-5 April 2014
5. Jayashree, H.V.; Agrawal, V.K.; Bharadwaj, N.S., "Post synthesis optimization of reversible logic functions with extended template matching," in Circuits, Communication, Control and Computing (I4C), 2014 International Conference on , vol., no., pp.368-371, 21-22 Nov. 2014
6. Jayashree, H.V.; Agarwal, V.K.; Charan, P.V.; Kariappa, A.M.C., "Design of fault tolerant n bit reversible comparator for optimization of garbage and Ancilla bits," in Circuits, Communication, Control and Computing (I4C), 2014 International Conference on , vol., no., pp.21-24, 21-22 Nov. 2014
H. V. Jayashree and K. Harsha, "Four BIT CMOS full adder in submicron technology with low leakage and Ground bounce noise reduction," Devices, Circuits and Systems (ICDCS), 2012 International Conference on, Coimbatore, 2012, pp. 20-24
7. Jayashree H V and S. Shruthi V P, "Ternary SRAM for low power applications," Communication, Information & Computing Technology (ICCICT), 2012 International Conference on, Mumbai, 2012, pp. 1-6
International Non-IEEE conferences
1. Jayashree HV, Phaneendra C H” Synchronous edge triggered counter with clock gating embedded into carry propagation”,N4C11,2011,RVCE,Bangalore.
2. Jayashree HV, Srisaila M Gowdar “Design and Verification of Ternary Arithmetic and
Shifter Unit”, CCCT2011,Aug 7-9, Delhi.
3. Jayashree HV, Puneeth B R “ Design and Verification of Ternary Co Processor”, ReSYM11, 2011, chennai.
1. Jayashree HV, Phaneendra C H “Double Edge Triggered Synchronous counter with clock
gating embedded into Carry propogation”, ICTI, 2011 ,Chennai
2. Jayashree HV,Sankar N “Design and implementation of Static Shifter with dynamic
shift index for location selection” Shri SSEC 2009, Bangalore .
3. Rakesh Bhimannavar, Jayashree HV,FPGA implementation of pipelined architecture for RC5.
"Growth of Technologies in Electronics, Computers and Telecom : Indian Perspective" (GTECT-2013) Mumbai. (Y.B. Chavan centre, near Nariman point) 29th september, 2013