Patent application number 3410/CHE/2014, Patent Filed on 09-07-2014
Digital Circuit Emulation and Simulation using Support Vector Machine (SVM) Classifiers.
The present subject matter relates to the use of set of binary Support Vector Machines (SVM) classifiers to represent and implement combinational circuit design. The combinational functionality is achieved by using a single binary SVM classifier for each bit of the output of the digital combinational function and each of these SVM classifiers would have the multiple inputs of the blocks. The parameters that characterize each of the SVM classifiers for that output bit is loaded into the memory of the SVM classifier apriori to the implementation for use. The functional aspect of the combined functional SVM classifier set is thus a function of the parameters loaded. Each functional combinational logic is to be achieved would only be characterized by the parameter set and the number of SVM classifiers used. A set of functional switches on the memory selection and output selection suitably synchronized over time can enable one binary SVM classifier to have multiple digital combinational functions.