Sudeendra Kumar K

Associate Professor

About

Sudeendra kumar K received B.E. from VTU and holds Masters and Doctoral Degrees from NIT Rourkela. He started his career with Wipro Biomed, Bangalore worked with Beckman Limited Equipment. His professional career includes a stint as Application Engineer for Freescale Semiconductors and Product Test Engineer for Qualcomm. He has got significant experience in Special Manpower Development Project -II (SMDP-II) and C2SD (SMDP-Chip to Systems Development) project under the aegis of Ministry of Communication and Information Technology, Govt. of India. He was responsible establishing VLSI labs, Training on EDA tools, chip design and tape out. He has got more than 30 publications in reputed journals and Conferences and also a reviewer for the Elsevier VLSI Integration Journal, IEEE Consumer Electronics Magazine and IEEE Transactions of Emerging Computing Systems. Currently, He is Joint Domain Head of VLSI and Embedded Systems in the Department of Electronics and Communication Engineering, PES University.

About

Education

B. E., VTU, Belgaum, 2004
M. Tech, National Institute of Technology, Rourkela, 2009
Ph. D, National Institute of Technology, Rourkela, 2019

Experience

Consultant Faculty- VLSI, National Institute of Technology, Rourkela, 2016 – 2019
Sr. Research Scholar, National Institute of Technology, Rourkela, 2013 – 2016
Product Test Engineer, Qualcomm, 2010 – 2012
Research Scholar, National Institute of Technology, Rourkela, 2006 – 2009
Application Engineer, G. T. Enterprises (Freescale Semiconductors), 2005 – 2006
Engineer, Wipro Biomed, 2004 – 2005

Additional Information

Actively participated in Debates related to Technology policy and Economic policy at NIT Rourkela
Invited as Keynote Speaker on “Hardware Trojans” in RISC Conference organized by Electronics For You magazine in 2017
Invited to speak on “IP Policy and Management” at TCS, Bhubaneshwar, 2018
Invited as Keynote Speaker on “Hardware Trojans” in RISC Conference organized by Electronics For You magazine in 2017
Invited to give lectures on “Hardware Security” and “Internet of Things” in various Govt. and Private organizations

Achievements

Best Paper Award in National Systems Conference -2008, at IIT, Roorkee
Best Paper Award in IEEE International Symposium on Nanoelectronics and Information Systems (iNIS), 2015, Indore
Best Paper Award in IEEE International Symposium on Nanoelectronics and Information Systems (iNIS), 2016, Gwalior

Teaching

CMOS Analog Integrated Circuits ( 2019-20)
Reconfigurable Computing (2019-20),
Formal Verification of Digital Design (2020-21)
Timing Analysis of Digital Circuits (2020-21)
Advanced Digital Design and Verification (2019-20)

Responsibilities

Teaching, Guiding students in projects, Facilitating research in VLSI and embedded systems
Domain Head (VLSI & Embedded Systems), Institute-Industry Relations, Curriculum Revision,
Domain Head of VLSI & Embedded Systems

Research Interests

Hardware Security
Lightweight Cryptography
ASIC Design
Processor Design

Conferences

1. Tarani Chaitanya Chinta, Sudeendra kumar K, K.K.Mahapatra, “Temperature Control using Controller Area Network”, International Conference on Microelectronics (ICONOME-08), Jan-2008, Pondicherry Engineering College, Pondicherry.
2. HCS08 Microcontroller based Novel PWM Controller for Battery Charger Application, Sudeendra kumar K, Ayas Kanta Swain, Sushant kumar pattnaik, K K Mahapatra IEEE Sponsored Conference on Computational Intelligence, Control and Computer Vision in Robotics & Automation, CICCRA March 10-11,2008.
3. Sudeendra kumar. K Leslin Varghese, K.K.Mahapatra, “Integrated control for Anti-lock brake system with collision avoidance using CAN for electric vehicles”, National Systems Conference, IIT Roorkee, Dec-2008. (Best Paper Award)
4. Sudeendra kumar .K, Leslin Varghese, K.K.Mahapatra, “Fuzzy logic based integrated control system for Anti-lock brake system with collision avoidance using CAN in electric vehicles”, IEEE International Conference on Industrial Technology, Monash University, Gippsland, Australia-Feb 2009.
5. Sagar Maliye; Pragyanpriyanka Satapathy; K. Sudeendra Kumar; Kamalakanta Mahapatra “Regenerative and Anti-Lock braking system in electric vehicles”, IEEE International Conference on Advanced Communication Control and Computing Technologies (ICACCCT)-2014
6. K. Sudeendra kumar, K Lodha, SR Sahoo, KK Mahapatra, “On-chip comparison based secure output response compactor for scan-based attack resistance” IEEE VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), Bangalore – 2015.
7. Kalpesh R. Lodha; Sudeendra kumar. K, K. K. Mahapatra, “A novel on-chip self-testing signature register for low cost manufacturing test” IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA),Bangalore, 2015.
8. K. Sudeendra Kumar, Rakesh Chanamala, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow. IEEE VLSI Design And Test, Nirma University, Ahmedabad, 2015.
9. Govinda Rao Locharla, K.Sudeendra Kumar, K. K. Mahapatra, Samit Ari: Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT. IEEEVLSI Design And Test (VDAT), Nirma University, Ahmedabad, 2015.
10. Sauvagya Ranjan Sahoo, K.Sudeendra Kumar, Kamalakanta Mahapatra: A novel ROPUF for hardware security. IEEEVLSI Design And Test (VDAT), Nirma University, Ahmedabad, 2015.
11. K Sudeendra Kumar, G Hanumantha Rao, Sauvagya Sahoo, K K Mahapatra, “A Novel PUF Based SST to Prevent Distribution of Rejected ICs from Untrusted Assembly”, IEEE International Symposium on Nanoelectronic and Information Systems-2015.
12. Sauvagya Ranjan Sahoo, K.Sudeendra Kumar, Kamalakanta Mahapatra “A Modified Configurable RO PUF with Improved Security Metrics” IEEE International Symposium on Nanoelectronic and Information Systems-2015. (Best Paper Award)
13. K Sudeendra Kumar, Naini Satheesh,Abhishek.Mahapatra, Sauvagya Sahoo, K K Mahapatra, “Securing IEEE 1687 Standard On-chip Instrumentation Access using PUF”, IEEE International Symposium on Nanoelectronic and Information Systems-2016. (Best Paper Award)
14. Naini Satheesh, Abhishek Mahapatra, Sudeendra kumar K, Sauvagya Sahoo, K.K.MahapatraA Modified RO-PUF with Improved Security Metrics on FPGA, IEEE International Symposium on Nanoelectronic and Information Systems-2016.
15. Sauvagya Ranjan Sahoo, K.Sudeendra Kumar, Kamalakanta Mahapatra “A Novel Aging Tolerant RO-PUF for Low Power Application” IEEE International Symposium on Nanoelectronic and Information Systems-2016.
16. Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, K. K. Mahapatra, “Analysis of Side-Channel Attack AES Hardware Trojan Benchmarks against Countermeasures”. IEEE International Symposium on VLSI, Bochum, Germany, (ISVLSI) – 2017: 574-579.
17. Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, K. K. Mahapatra, “A Flexible Pay-per-Device Licensing Scheme for FPGA IP Cores”. IEEE International Symposium on VLSI, Bochum, Germany, (ISVLSI)-2017: 677-682.
18.Sudeendra Kumar K, Saurabh Seth, Sauvagya Ranjan Sahoo, Abhishek Mahapatra, Ayas Kanta Swain, Kamalakanta Mahapatra, “PUF-Based Secure Test Wrapper for SoC Testing”. IEEE International Symposium on VLSI (ISVLSI), Hong Kong, 2018: 672-677.
Manoj Kumar JYV, Ayas Kanta Swain, Sudeendra Kumar K, Sauvagya Ranjan Sahoo, Kamalakanta Mahapatra, “Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip”. IEEE International Symposium on VLSI (ISVLSI)-, Hong Kong, 2018: 738-743, 2017.
20. Sudeendra kumar K, S. R. Sahoo, Krishna Kiran, A. K. Swain, K. K. Mahapatra, “A Novel Holistic Security Framework for In-field Firmware”, IEEE International Symposium on Smart Electronic Systems, Hyderabad, India, 2018, 261-264.
21. S.K. Ram, S. R. Sahoo, Sudeendra kumar, Kamalakanta Mahapatra, “Energy Efficient Ultra Low Power Solar Harvesting System Design with MPPT”, IEEE International Symposium on Smart Electronic Systems, Hyderabad, India, 2018, 130-133.

Journals

1. K. Sudeendra kumar et, al,”Secure split techniques to prevent IC piracy for IoT devices”, Journal of VLSI Integration, Elsevier, Vol.58, Pages 390-400, June 2017.
2. Govinda Rao Locharla, K. Sudeendra Kumar, Kamala Kanta Mahapatra, Samit Ari: Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT. IET Computers & Digital Techniques 10(5): 215-225 (2016).
3. Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra “A novel current controlled configurable RO PUF with improved security metrics”, Journal of VLSI Integration, Elsevier, pages 401-410, June- 2017.
4. Sudeendra kumar K, et al “Supply Voltage Scaling based Novel CRO PUF with Improved Reliability” Journal of Microprocessor and Microsystems, Elsevier, Vol. 60, pages 40-52, July 2018.
5. Sudeendra kumar K, et al “Securing Access to IEEE 1687 On-chip Instrumentation using PUF”, IEEE Consumer Electronics Magazine, Vol. 8, Issue 4, pages 62-66, July 2019
6. Sahoo, S.R., Kumar, S. & Mahapatra, K. A novel reliable and aging tolerant modified RO PUF for low power application. Analog Integr Circ Sig Process 103, 493-509 (2020).