Dhanashree G Bhate
Dhanashree G Bhate
Assistant Professor
Assistant Professor
Education
- B.E. (EEE), Gogte Institute of Technology , Belgaum ( Karnatak University Dharwad), 2001
- M. Tech ( VLSI Design & Embedded Systems), B.M.S. College of Engineering , Bangalore, 2010
- Ph.D ( Persuing), PES Institute of Technology Bangalore ( VTU research center)
Experience
- Trainee Engineer, Indian Institute of Astrophysics Bangalore, 2001 – 2005
- Lecturer, Dayanand Sagar College of Engineering , Bangalore, 2005 – 2006
- Assistant Professor, PES Institutions, August 2006 – Till Today 2021
Achievements
- B.E. 1st Rank to college (G.I.T Belgaum), 4th Rank Karnatak University Dharwad
- Distinction Holder
Teaching
- Basic Electrical Engineering
- Digital design / Logic Design Theory & Lab
- Hardware Descriptive language using VHDL & Verilog Theory & Lab
- Embedded systems Theory
- Computer Organization & Digital Design Theory & Lab
- Digital System design Using VHDL
- Digital System Design Using Xilinx Vivado Design tool ( Special topic)
Responsibilities
- Mentoring Coordinator for department
Research Interests
- VLSI Design , Motor Control , FPGA
Conferences
- Dhanashree Bhate ; Shashidhar Tantry; Jayanth Gopinath; Kumara A. Naveen Implementation of DC Motor Speed Control Logic on FPGA,2018 3rd International Conference for Convergence in Technology (I2CT), Year: 2018, Conference Paper, Publisher: IEEE
Education
- B.E. (EEE), Gogte Institute of Technology , Belgaum ( Karnatak University Dharwad), 2001
- M. Tech ( VLSI Design & Embedded Systems), B.M.S. College of Engineering , Bangalore, 2010
- Ph.D ( Persuing), PES Institute of Technology Bangalore ( VTU research center)
Experience
- Assistant Professor, PES University, August-2021 – Till Date
- Assistant Professor, Vemana Institute of Technology, July-2011 – July-2021
- Lecturer, Vemana Institute of Technology, Jan-2008 – June-2009
Achievements
- B.E. 1st Rank to college (G.I.T Belgaum), 4th Rank Karnatak University Dharwad
- Distinction Holder
Teaching
- Basic Electrical Engineering
- Digital design / Logic Design Theory & Lab
- Hardware Descriptive language using VHDL & Verilog Theory & Lab
- Embedded systems Theory
- Computer Organization & Digital Design Theory & Lab
- Digital System design Using VHDL
- Digital System Design Using Xilinx Vivado Design tool ( Special topic)
Responsibilities
- Mentoring Coordinator for department
Research Interests
- VLSI Design , Motor Control , FPGA
Conferences
- Dhanashree Bhate ; Shashidhar Tantry; Jayanth Gopinath; Kumara A. Naveen Implementation of DC Motor Speed Control Logic on FPGA,2018 3rd International Conference for Convergence in Technology (I2CT), Year: 2018, Conference Paper, Publisher: IEEE
Staff Contacts
Staff Contacts
- 8026721983
- dhanashreegb@pes.edu
- Electronics & Communications
- 8026721983
- dhanashreegb@pes.edu
- Electronics & Communications
- EC Campus
- EC Campus