Pavithra Y J
Pavithra Y J
Assistant Professor
Assistant Professor
About
Is working as Assistant Professor in Department of Electronics and Communiction Engineering since 2007. B.E -Electronics and Communicaton Engineering from Kuvempu University M.Tech- Specialization in Electronics from VTU, Belagavi Ph.D-Pursuing
About
Is working as Assistant Professor in Department of Electronics and Communiction Engineering since 2007. B.E -Electronics and Communicaton Engineering from Kuvempu University M.Tech- Specialization in Electronics from VTU, Belagavi Ph.D-Pursuing
Education
- M.Tech(Electronics), Sir MVIT, Bangalore, 2007
Experience
- Assistant Professor, PES University, 2007 – Till date
Achievements
- 2nd Rank in M.Tech, VTU
Teaching
- Keeps interest in the field of Embedded Systems and has handled various subjects in the domain for both UG and PG
- Subject interests are Digital Electronics, Microcontroller/processor, Embedded System Design, Computer Organization, Computer Aided Digital Design,Real Time Operating Systems,Real Time Embedded System etc
Responsibilities
- Keeps interest in the field of Embedded Systems and has handled various subjects in the domain for both UG and PG
- Subject interests are Digital Electronics, Microcontroller/processor, Embedded System Design, Computer Organization, Computer Aided Digital Design,Real Time Operating Systems,Real Time Embedded System etc
Research Interests
- Is part of the VLSI Domain and working to pursue Ph.D in the domain of Embedded Systems .
Research Projects
- Digital Circuit Optimization, Evolutionary algorithm, Memory-Performance
Research Guidance
- Have been handling projects in the areas of digital circuit optimization, performance improvement of memory
Conferences
- Study and Evaluation of Digital Circuit Design Using Evolutionary Algorithm 2018 15th IEEE India Council International Conference (INDICON)
- Hardware Resource Optimization for Embedded System Design: A Brief Review 2018 3rd International Conference for Convergence in Technology (I2CT)
- Improved Cache replacement policy based on recency time re-reference interval prediction 2022 IEEE International conference I2CT, 2022
- Review of Cache Performance Improvement Techniques IEEE International conference ICECIM, 2021
- Design of Combinational Logic Circuits using simulated annealing, IEEE International conference ICONAT 2022
Others
- ” An FPGA based radar target generator” , CISCON 2007
- “Denoising medical ultrasound images using wavelet domain Bayesian processor”, CISCON 2009
- “Mosaicing of Images: Novel Approach based on Texture Features”, CISCON 2009
- “Mosaicing of Images: Novel Approach based on Edge Patterns”, CISCON 2009
- “Implementation of Scale Invariant Feature Transform on FPGA”, MICROCOM 2016
Education
- M.Tech(Electronics), Sir MVIT, Bangalore, 2007
Experience
- Assistant Professor, PES University, 2007 – Till date
Achievements
- 2nd Rank in M.Tech, VTU
Teaching
- Keeps interest in the field of Embedded Systems and has handled various subjects in the domain for both UG and PG
- Subject interests are Digital Electronics, Microcontroller/processor, Embedded System Design, Computer Organization, Computer Aided Digital Design,Real Time Operating Systems,Real Time Embedded System etc
Responsibilities
- Has handled various departmental activities and has been part of organizing various workshops, pre-placement activity, faculty development programmes and conference.
- Assistant Professor
Research Interests
- Is part of the VLSI Domain and working to pursue Ph.D in the domain of Embedded Systems .
Research Projects
- Digital Circuit Optimization, Evolutionary algorithm, Memory-Performance
Research Gudiance
- Have been handling projects in the areas of digital circuit optimization, performance improvement of memory
Conferences
- Study and Evaluation of Digital Circuit Design Using Evolutionary Algorithm 2018 15th IEEE India Council International Conference (INDICON)
- Hardware Resource Optimization for Embedded System Design: A Brief Review 2018 3rd International Conference for Convergence in Technology (I2CT)
- Improved Cache replacement policy based on recency time re-reference interval prediction 2022 IEEE International conference I2CT, 2022
- Review of Cache Performance Improvement Techniques IEEE International conference ICECIM, 2021
- Design of Combinational Logic Circuits using simulated annealing, IEEE International conference ICONAT 2022
Others
- ” An FPGA based radar target generator” , CISCON 2007
- “Denoising medical ultrasound images using wavelet domain Bayesian processor”, CISCON 2009
- “Mosaicing of Images: Novel Approach based on Texture Features”, CISCON 2009
- “Mosaicing of Images: Novel Approach based on Edge Patterns”, CISCON 2009
- “Implementation of Scale Invariant Feature Transform on FPGA”, MICROCOM 2016
Staff Contacts
Staff Contacts
- 8026721983
- pavitra.yj@pes.edu
- Electronics & Communications
- 8026721983
- pavitra.yj@pes.edu
- Electronics & Communications
- RR Campus
- RR Campus