Raghavendra M
Raghavendra M
Assistant Professor
Assistant Professor
Education
- M.Tech in Digital Electronics and Advanced Communication, Manipal Institute of Technology, Manipal University, 2008
- B.E, PES Institute of Technology, 2005
Experience
- Assiatant Professor, SBMICE, Jain University, 2010 – 2011
- Assiatant professor, PES University, 2011 – Till Date
Achievements
- Workshop conducted on VHDL & FPGA for Scientist-F team of DRDO during July 2013
- Workshop conducted on VLSI & Embedded System Design in coordination with Sparsh Technologies during July 2012
Teaching
- Analog Circuits Design
- Microelectronics Circuit
- Digital CMOS VLSI Design
- Network Analysis
- Hardware Description Language (HDL)
- AEC Lab
- HDL Lab
- VLSI Lab
- Linear Integrated Circuits Lab
Responsibilities
- PESU Academy Coordinator
Conferences
- Hazrath Patil, M Raghavendra, ?Low power dynamic compactor for 4 bit Flash ADC, International Journal of Service Computing And Computational Intelligence , ICCIC1600104 -Best Paper Awarded
- Rahul P V, Anusha Kulkarni, Sohail Sankanur and Raghavendra M, Reduced Comparators for Low Power Flash ADC using TSMC018, International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS )
- Rohit J, Raghavendra M, ?Implementation of 32-bit RISC processors without interlocked Pipelining on Artix-7 FPGA Board, 2017 International Conference on Circuits, Controls, and Communications (CCUBE 2017)
Education
- M.Tech in Digital Electronics and Advanced Communication, Manipal Institute of Technology, Manipal University, 2008
- B.E, PES Institute of Technology, 2005
Experience
- Assiatant Professor, SBMICE, Jain University, 2010 – 2011
- Assiatant professor, PES University, 2011 – Till Date
Achievements
- Workshop conducted on VHDL & FPGA for Scientist-F team of DRDO during July 2013
- Workshop conducted on VLSI & Embedded System Design in coordination with Sparsh Technologies during July 2012
Teaching
- Analog Circuits Design
- Microelectronics Circuit
- Digital CMOS VLSI Design
- Network Analysis
- Hardware Description Language (HDL)
- AEC Lab
- HDL Lab
- VLSI Lab
- Linear Integrated Circuits Lab
Responsibilities
- PESU Academy Coordinator
Conferences
- Hazrath Patil, M Raghavendra, ?Low power dynamic compactor for 4 bit Flash ADC, International Journal of Service Computing And Computational Intelligence , ICCIC1600104 -Best Paper Awarded
- Rahul P V, Anusha Kulkarni, Sohail Sankanur and Raghavendra M, Reduced Comparators for Low Power Flash ADC using TSMC018, International Conference on Microelectronic Devices, Circuits and Systems (ICMDCS )
- Rohit J, Raghavendra M, ?Implementation of 32-bit RISC processors without interlocked Pipelining on Artix-7 FPGA Board, 2017 International Conference on Circuits, Controls, and Communications (CCUBE 2017)
Staff Contacts
Staff Contacts
- 8026721983
- raghavendrame@pes.edu
- Electronics & Communications
- 8026721983
- raghavendrame@pes.edu
- Electronics & Communications
- EC Campus
- EC Campus