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Dr. Nirmala Devi M

Dr. Nirmala Devi M

Dr. Nirmala Devi M

Professor

Professor

About

Full Professor with 27+ years of academic experience with Amrita Vishwa Vidyapeetham Having significant contribution in the domain of VLSI System Design, Testing and Hardware Security Research Looking for career enhancement with the major focus on Research Mentorship and Execution for enriching research blended learning for Academic excellence.

About

Full Professor with 27+ years of academic experience with Amrita Vishwa Vidyapeetham Having significant contribution in the domain of VLSI System Design, Testing and Hardware Security Research Looking for career enhancement with the major focus on Research Mentorship and Execution for enriching research blended learning for Academic excellence.

Education

  • Ph. D., Anna University – Government College of Technology, Coimbatore, 2010

Experience

  • Lecturer – Professor, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, 1996 – 2023

Additional Information

  • Professor, Department of ECE

Achievements

  • Involved in the development of side channel analysis and Machine learning based Hardware Trojan Detection schemes. • Quality publications in Q1 journals including IEEE Transactions and well reputed conferences including VLSID & VDAT
  •  Served as PI, Co-PI and Team member of various funded R&D projects in Computational Intelligence and hardware security domain • Established Hardware Security Funded lab setup aided by DRDO

Teaching

  • Digital CMOS Integrated Circuits, VLSI Design and Testing, Hardware Security and Verification, Electronic Devices and Crcuits, Analog & Linear Integrated Circuits, Digital VLSI Design, Microprocessors, Analog Communication Engineering, Digital System Design

Research Interest

  • VLSI Systems Design and Testing, Hardware Security of System-on- chip, Design for Security, Machine Learning, Computational Intelligence
  • VLSI Systems Design and Testing, Hardware Security of System-on- chip, Design for Security, Machine Learning, Computational Intelligence

Research Projects

  • Automated structural evolution and performance Optimization of RF band passes filter – An Evolutionary Algorithmic Design Approach (ISRO/RES/3//18-19),
  • Capacity, bit error rate and performance evaluation of MIMO based Communication System on Minimized Multipath Environment, (ISRO/RES/3/740/17-18)
  • Hardware Trojan Detection and Consistency based Analysis, (ERIP/ER/1503187/M/01/1582) Principal Investigator: Dr. Nirmala Devi M , Period: Two Years, Nov 2015- Nov 2017, Date of Completion: 31 March 2018 Amount: Rs. 23.457, Agency: DRDO, SAG – Delhi
  • Predictive Fault Diagnosis in Nuclear Power Plants Using Deep Learning Techniques,, (59/14/03/2019-BRNS/34090),

Research Guidance

  • M. Priyatharishini, Pre-Silicon Hardware Trojan Detection to Enhance Security in VLSI Circuits Using Computational Intelligence Algorithms , 12 December 2023
  • Arun Kumar Sundar Rajan , Implementation and Evaluation of Hypervisor for Automotive Heterogeneous Hard Real-Time Embedded Applications on A Multicore Platform, 12 February 2021.
  • R. Sree Ranjani, Enhanced Hardware Trojan Detection and Prevention Techniques To Ensure A Secured Hardware With Improved Performance Metrics, 10 May 2019
  • Ramesh Bhakthavatchalu, A Reconfigurable Logic BIST Architecture For Secure Testing of VLSI Circuits, 22 February 2016

Conferences

  • Sahana, C., Nirmala Devi, M., Jayakumar, M. Unconventional Structure Based Dual-band Circularly Polarized Microstrip Antenna for GAGAN Receivers INDICON 2022 – 2022 IEEE 19th India Council International Conference, 2022
  • Vaishnavi Sankar, Nirmala Devi, M., Jayakumar, M. Hardware Trojan Detection and Diagnosis through Synthesis and Validation using Game Theory INDICON 2022 – 2022 IEEE 19th India Council International Conference, 2022.
  • Sankar, V., Balachander Sathianarayanan, Nirmala Devi, M., Jayakumar, M., Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique, January 2023, 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID). DOI: 10.1109/VLSID57277.2023.00079

Journals

  • Karthigha Balamurugan, Nirmala Devi, M., Jayakumar, M., Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors, August 2023, Journal of Electrical and Computer Engineering 2023(1):1-15 (IF: 2.4, Scopus % : 62, h-index:34, Q2), DOI: 10.1155/2023/2469673
  • Sankar, V., Nirmala Devi, M., Jayakumar, M. Guided Data Augmentation Scheme Combined with Adaptive Evolutionary Algorithm for Hardware Trojan Detection to Enhance Communication Security, International Journal on Communications Antenna and Propagation, 2022, 12(4), pp. 251–260 . (Scopus IF: 1.495, Scopus%: 68) DOI: https://doi.org/10.15866/irecap.v12i4.21578
  • Sundar Rajan, A.K., Nirmala Devi, M., Software-Based Approach for Sharing Real- Time Peripherals in a Virtualized Automotive Microcontroller Platform , SAE International Journal of Connected and Automated Vehicles , 2021, 4(2), pp. 205– 220 DOI 10.4271/12-04-02-0016
  • Ankathi, S., Vignan, S., Athukuri, S., …Balamurugan, K., Nirmala Devi, M., A 5– 7 GHz current reuse and gm-boosted common gate low noise amplifier with LC based ESD protection in 32 nm CMOS, Analog Integrated Circuits and Signal Processing, March 2017, 90(3), pp. 573–589. (IF: 1.321, Scopus%: 41, hindex :51) , DOI 10.1007/s10470-016-0915-x
  • Sundar Rajan, A.K., Feucht, A., Gamer, L., Smaili, I., M., Nirmala Devi., M., Hypervisor for consolidating real-time automotive control units: Its procedure, implications and hidden pitfalls, Journal of Systems Architecture, Jan 2018, 82, pp. 37–48 (IF: 5.836, Scopus % : 79, hindex:53), DOI 10.1016/j.sysarc.2018.01.001
  • Ganesan, M., Lavanya, R., Nirmala Devi, M., , Fault detection in satellite power system using convolutional neural network, Telecommunication Systems, April 2021, 76(4), pp. 505–511 (IF:2.33 , Scopus % : 71, hindex: 54), DOI 10.1007/s11235-020-00722-5.
  • Shiny, M.I., Nirmala Devi, M., Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application, Mobile Networks and Applications, 2022, 27(3), pp. 1000–1018 (IF: 3.662 Scopus %: 82, h index :89), DOI 10.1007/s11036-021-01857-8
  • Sahana, C., Nirmala Devi, M., Jayakumar, M., Dual-Band Circularly Polarized Annular Ring Patch Antenna for GPS-Aided GEO-Augmented Navigation Receivers, IEEE Antennas and Wireless Propagation Letters, Sept. 2022, 21(9), pp. 1737–1741 ( IF: 3.825, Scopus: 87%, h index :126), DOI 10.1109/LAWP.2022.3178980
  • Rajat Subhra Chakraborty ; Samuel Pagliarini ; Jimson Mathew ; Sree Ranjani Rajendran ; M. Nirmala Devi, A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis, IEEE Transactions on Emerging Topics in Computing 5(2),7820075, pp. 260-270, 2017 (IF: 6.595, Scopus%: 92, h index : 48). DOI 10.1109/TETC.2017.2654268
  • Priyatharishini, M., Nirmala Devi, M., A deep learning based malicious module identification using stacked sparse auto- encoder network for VLSI circuit reliability, Measurement: Journal of the International Measurement Confederation, 2022, 194, 111055 (IF: 5.131, Scopus % : 95), https://doi.org/10.1016/j.measurement.2022.111055
  • Sahana, C., Nirmala Devi, M., Jayakumar, M., Hexagonal-Triangular Co mbinatorial Structure Based Dual-Band Circularly Polarized Patch Antenna for GAGAN Receivers, January 2023, IEEE Access, 11, PP 23205 – 23216, DOI: 10.1109/ACCESS.2023.3252913
  • Shiny, M.I., Nirmala Devi, M., PUF Based on Chip Comparison Technique for Trustworthy Scan Design Data Security against Side Channel Attack, International Journal of Cloud Computing 12(2/3/4):1, January 2023, DOI: 10.1504/IJCC.2023.10053098.
  • Vaishnavi Sankar, Nirmala Devi, M., Jayakumar, M., Data Augmented Hardware Trojan Detection Using Label Spreading Algorithm Based Transductive Learning for Edge Computing-Assisted IoT Devices, IEEE Access, 2022, 10, pp. 102789–102803 (IF:3.476, Scopus%: 90%, h-index:158), DOI:10.1109/ACCESS.2022.3209705
  • Balachander Sathianarayanan, Singh Samant, Y.C., Conjeepuram Guruprasad, P.S., Hariharan, V.B., Nirmala Devi M., Feature-based augmentation and classification for tabular data, CAAI Transactions on Intelligence Technology, 2022, 7(3), pp. 481–491. (IF: 7.985, Scopus%: 92, h index : 21 ). https://doi.org/10.1049/cit2.12123
  • M. Nirmala Devi, Vaishnavi Sankar., Graph Based Heterogeneous Feature Extraction for Enhanced Hardware Trojan Detection at Gate-Level Using Optimized Xgboost Algorithm, Measurement: Journal of the International Measurement Confederation, Volume 220, October 2023, 113320 (IF: 5.7, Scopus % : 95), https://doi.org/10.1016/j.measurement.2023.113320

Books

  • Sree Ranjani Rajendran, Nirmala Devi , M, M Jayakumar, A Node Reduction Technique for Trojan Detection and Diagnosis in IoT Hardware Devices, Internet of Things, March 2022, pp.43-64. DOI: 10.1201/9781003219620-3

Others

  • Kumar, B.P., Nirmala Devi, M , An Effective Logic Obfuscation Technique with AES Encryption Module for Design Protection, Lecture Notes in Networks and Systems, 2020, 98, pp. 18–28.
  • Shashank Pathak, Nirmala Devi M., Preventing Data Leakage by Trojans in Commercial and ASIC Applications Using TDM and DES Encryption and Decryption, In book: Advanced IoT Sensors, Networks and Systems, June 2023 DOI: 10.1007/978-981-99-1312-1_8
  • Sundar Rajan, A.K., Nirmala Devi, M , Virtualizing an Automotive State-of-the-Art Microcontroller: Techniques and Its Evaluation, EAI/Springer Innovations in Communication and Computing, 2021, pp. 19–36. DOI :10.1007/978-3-030-59897- 6_2

Education

  • Ph. D., Anna University – Government College of Technology, Coimbatore, 2010

Experience

  • Lecturer – Professor, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, 1996 – 2023

Additional Information

  • Professor, Department of ECE

Achievements

  • Involved in the development of side channel analysis and Machine learning based Hardware Trojan Detection schemes. • Quality publications in Q1 journals including IEEE Transactions and well reputed conferences including VLSID & VDAT
  •  Served as PI, Co-PI and Team member of various funded R&D projects in Computational Intelligence and hardware security domain • Established Hardware Security Funded lab setup aided by DRDO

Teaching

  • Digital CMOS Integrated Circuits, VLSI Design and Testing, Hardware Security and Verification, Electronic Devices and Crcuits, Analog & Linear Integrated Circuits, Digital VLSI Design, Microprocessors, Analog Communication Engineering, Digital System Design

Research Interest

  • VLSI Systems Design and Testing, Hardware Security of System-on- chip, Design for Security, Machine Learning, Computational Intelligence
  • VLSI Systems Design and Testing, Hardware Security of System-on- chip, Design for Security, Machine Learning, Computational Intelligence

Research Projects

  • Automated structural evolution and performance Optimization of RF band passes filter – An Evolutionary Algorithmic Design Approach (ISRO/RES/3//18-19),
  • Capacity, bit error rate and performance evaluation of MIMO based Communication System on Minimized Multipath Environment, (ISRO/RES/3/740/17-18)
  • Hardware Trojan Detection and Consistency based Analysis, (ERIP/ER/1503187/M/01/1582) Principal Investigator: Dr. Nirmala Devi M , Period: Two Years, Nov 2015- Nov 2017, Date of Completion: 31 March 2018 Amount: Rs. 23.457, Agency: DRDO, SAG – Delhi
  • Predictive Fault Diagnosis in Nuclear Power Plants Using Deep Learning Techniques,, (59/14/03/2019-BRNS/34090),

Research Guidance

  • M. Priyatharishini, Pre-Silicon Hardware Trojan Detection to Enhance Security in VLSI Circuits Using Computational Intelligence Algorithms , 12 December 2023
  • Arun Kumar Sundar Rajan , Implementation and Evaluation of Hypervisor for Automotive Heterogeneous Hard Real-Time Embedded Applications on A Multicore Platform, 12 February 2021.
  • R. Sree Ranjani, Enhanced Hardware Trojan Detection and Prevention Techniques To Ensure A Secured Hardware With Improved Performance Metrics, 10 May 2019
  • Ramesh Bhakthavatchalu, A Reconfigurable Logic BIST Architecture For Secure Testing of VLSI Circuits, 22 February 2016

Conferences

  • Sahana, C., Nirmala Devi, M., Jayakumar, M. Unconventional Structure Based Dual-band Circularly Polarized Microstrip Antenna for GAGAN Receivers INDICON 2022 – 2022 IEEE 19th India Council International Conference, 2022
  • Vaishnavi Sankar, Nirmala Devi, M., Jayakumar, M. Hardware Trojan Detection and Diagnosis through Synthesis and Validation using Game Theory INDICON 2022 – 2022 IEEE 19th India Council International Conference, 2022.
  • Sankar, V., Balachander Sathianarayanan, Nirmala Devi, M., Jayakumar, M., Reliability Enhancement of Hardware Trojan Detection using Histogram Augmentation Technique, January 2023, 2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID). DOI: 10.1109/VLSID57277.2023.00079

Journals

  • Karthigha Balamurugan, Nirmala Devi, M., Jayakumar, M., Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors, August 2023, Journal of Electrical and Computer Engineering 2023(1):1-15 (IF: 2.4, Scopus % : 62, h-index:34, Q2), DOI: 10.1155/2023/2469673
  • Sankar, V., Nirmala Devi, M., Jayakumar, M. Guided Data Augmentation Scheme Combined with Adaptive Evolutionary Algorithm for Hardware Trojan Detection to Enhance Communication Security, International Journal on Communications Antenna and Propagation, 2022, 12(4), pp. 251–260 . (Scopus IF: 1.495, Scopus%: 68) DOI: https://doi.org/10.15866/irecap.v12i4.21578
  • Sundar Rajan, A.K., Nirmala Devi, M., Software-Based Approach for Sharing Real- Time Peripherals in a Virtualized Automotive Microcontroller Platform , SAE International Journal of Connected and Automated Vehicles , 2021, 4(2), pp. 205– 220 DOI 10.4271/12-04-02-0016
  • Ankathi, S., Vignan, S., Athukuri, S., …Balamurugan, K., Nirmala Devi, M., A 5– 7 GHz current reuse and gm-boosted common gate low noise amplifier with LC based ESD protection in 32 nm CMOS, Analog Integrated Circuits and Signal Processing, March 2017, 90(3), pp. 573–589. (IF: 1.321, Scopus%: 41, hindex :51) , DOI 10.1007/s10470-016-0915-x
  • Sundar Rajan, A.K., Feucht, A., Gamer, L., Smaili, I., M., Nirmala Devi., M., Hypervisor for consolidating real-time automotive control units: Its procedure, implications and hidden pitfalls, Journal of Systems Architecture, Jan 2018, 82, pp. 37–48 (IF: 5.836, Scopus % : 79, hindex:53), DOI 10.1016/j.sysarc.2018.01.001
  • Ganesan, M., Lavanya, R., Nirmala Devi, M., , Fault detection in satellite power system using convolutional neural network, Telecommunication Systems, April 2021, 76(4), pp. 505–511 (IF:2.33 , Scopus % : 71, hindex: 54), DOI 10.1007/s11235-020-00722-5.
  • Shiny, M.I., Nirmala Devi, M., Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application, Mobile Networks and Applications, 2022, 27(3), pp. 1000–1018 (IF: 3.662 Scopus %: 82, h index :89), DOI 10.1007/s11036-021-01857-8
  • Sahana, C., Nirmala Devi, M., Jayakumar, M., Dual-Band Circularly Polarized Annular Ring Patch Antenna for GPS-Aided GEO-Augmented Navigation Receivers, IEEE Antennas and Wireless Propagation Letters, Sept. 2022, 21(9), pp. 1737–1741 ( IF: 3.825, Scopus: 87%, h index :126), DOI 10.1109/LAWP.2022.3178980
  • Rajat Subhra Chakraborty ; Samuel Pagliarini ; Jimson Mathew ; Sree Ranjani Rajendran ; M. Nirmala Devi, A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis, IEEE Transactions on Emerging Topics in Computing 5(2),7820075, pp. 260-270, 2017 (IF: 6.595, Scopus%: 92, h index : 48). DOI 10.1109/TETC.2017.2654268
  • Priyatharishini, M., Nirmala Devi, M., A deep learning based malicious module identification using stacked sparse auto- encoder network for VLSI circuit reliability, Measurement: Journal of the International Measurement Confederation, 2022, 194, 111055 (IF: 5.131, Scopus % : 95), https://doi.org/10.1016/j.measurement.2022.111055
  • Sahana, C., Nirmala Devi, M., Jayakumar, M., Hexagonal-Triangular Co mbinatorial Structure Based Dual-Band Circularly Polarized Patch Antenna for GAGAN Receivers, January 2023, IEEE Access, 11, PP 23205 – 23216, DOI: 10.1109/ACCESS.2023.3252913
  • Shiny, M.I., Nirmala Devi, M., PUF Based on Chip Comparison Technique for Trustworthy Scan Design Data Security against Side Channel Attack, International Journal of Cloud Computing 12(2/3/4):1, January 2023, DOI: 10.1504/IJCC.2023.10053098.
  • Vaishnavi Sankar, Nirmala Devi, M., Jayakumar, M., Data Augmented Hardware Trojan Detection Using Label Spreading Algorithm Based Transductive Learning for Edge Computing-Assisted IoT Devices, IEEE Access, 2022, 10, pp. 102789–102803 (IF:3.476, Scopus%: 90%, h-index:158), DOI:10.1109/ACCESS.2022.3209705
  • Balachander Sathianarayanan, Singh Samant, Y.C., Conjeepuram Guruprasad, P.S., Hariharan, V.B., Nirmala Devi M., Feature-based augmentation and classification for tabular data, CAAI Transactions on Intelligence Technology, 2022, 7(3), pp. 481–491. (IF: 7.985, Scopus%: 92, h index : 21 ). https://doi.org/10.1049/cit2.12123
  • M. Nirmala Devi, Vaishnavi Sankar., Graph Based Heterogeneous Feature Extraction for Enhanced Hardware Trojan Detection at Gate-Level Using Optimized Xgboost Algorithm, Measurement: Journal of the International Measurement Confederation, Volume 220, October 2023, 113320 (IF: 5.7, Scopus % : 95), https://doi.org/10.1016/j.measurement.2023.113320

Books

  • Sree Ranjani Rajendran, Nirmala Devi , M, M Jayakumar, A Node Reduction Technique for Trojan Detection and Diagnosis in IoT Hardware Devices, Internet of Things, March 2022, pp.43-64. DOI: 10.1201/9781003219620-3

Others

  • Kumar, B.P., Nirmala Devi, M , An Effective Logic Obfuscation Technique with AES Encryption Module for Design Protection, Lecture Notes in Networks and Systems, 2020, 98, pp. 18–28.
  • Shashank Pathak, Nirmala Devi M., Preventing Data Leakage by Trojans in Commercial and ASIC Applications Using TDM and DES Encryption and Decryption, In book: Advanced IoT Sensors, Networks and Systems, June 2023 DOI: 10.1007/978-981-99-1312-1_8
  • Sundar Rajan, A.K., Nirmala Devi, M , Virtualizing an Automotive State-of-the-Art Microcontroller: Techniques and Its Evaluation, EAI/Springer Innovations in Communication and Computing, 2021, pp. 19–36. DOI :10.1007/978-3-030-59897- 6_2

Staff Contacts

Staff Contacts

  • 8026721983
  • nirmaladevim@pes.edu
  • Electronics & Communications
  • 8026721983
  • nirmaladevim@pes.edu
  • Electronics & Communications
  • RR Campus
  • RR Campus

Staff Campus Location

Staff Campus Location

100 Feet Ring Road,
BSK III Stage,
Bangalore-560085

  • +91 80 26721983
  • +91 80 26722108

For Admissions

  • 080-10-297297
  • admissions@pes.edu
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Information For

Information About

Important Info

Information For

Information About

Important Info

100 Feet Ring Road,
BSK III Stage,
Bangalore-560085

For Admissions

  • 080-10-297297
  • admissions
    @pes.edu
  • +91 80 26721983
  • +91 80 26722108
Facebook-f Linkedin-in Twitter Youtube Instagram
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